Especially for ESD Protection devices, the newly released package based on a Laminate Grid Array (LGA) technology in combination with a flip chip (FC) die attached offers some benefits compared to the standard DFN package platform. This advantage can be demonstrated very well considering the S-Parameter - whose basic theory we described in a previous blog post (See: Why Flip-Chip LGA is a Game Changer for RF ESD Protection).
ESD Protection devices protect data lines, and a good data transfer on these interfaces strongly depends on the losses in the path. It is the nature of ESD protection devices that they come with some capacitances that create speed limitations of the maximum applicable speed for data transmission. The junction of the semiconductor structure itself causes this capacitance. During previous years, the development of new discrete ESD protection devices concentrated on the reduction of this capacitance, and these efforts were quite successful. At the beginning of the 2010s, a good ESD protection device for USB Interfaces, which was capable of sustaining 15 kV, came along with a typical junction capacitance of 1.5 pF, whereas nowadays, the range of 15 kV capable devices has typical values down to 0.15 pF.
In addition to the junction capacitances, there are more unwanted influences on the data transmission caused by the package of the ESD protection device that have become more important nowadays due to two different causes. First of all, if the junction capacitance is in the same order of magnitude as the parasitic package capacitance, the influence of the package becomes visible. Secondly, high-speed data enters more and more of the application fields in the automotive world. Bare die solutions, while effective in the mobile and computing sectors, are not suitable or accepted for the harsh conditions encountered in automotive applications. Molded devices that offer this higher environmental protection are still needed.
The key to solving this problem is the development of new packages offering small parasitic capacitances for discrete ESD protection devices. In addition to the low capacitance, a small inductance helps to improve data transmission, and this requirement was considered to improve Nexperia products.
The capability of data transmission in the time domain can be directly transformed to the requirements of a high bandwidth in the frequency domain, as can be seen in S-Parameter plots.
FCLGA vs DFN for 5 V VRWM Types
It is difficult to compare the performance of different packages based solely on package design. Other parameters, such as semiconductor process and die design, are intertwined with the package and influence performance improvement.
Insertion Loss
In Figure 2a, you can see the comparison of the Insertion Loss, also called S21, of PESD5V0H1BLG-Q in FCLGA technology and a PESD5V0C1BLS-Q based on DFN. They share the same silicon process, package size, junction capacitance, and ESD level. The principal measurement setup is done with Z-Probes on a PCB. More details on that can be found in our first blog which covers the basics of S-Parameters.
In Figure 2b, two multi-pin devices are compared. PESD4USB5BTBS-Q is a 10-pin device in DFN technology. To compare its performance with a 3-pin device, only pins 1 and 2 are taken into consideration. It is compared to the PESD5V0H2BFG-Q from the FCLGA platform.
Table 1 clearly shows that for both packages, the SE bandwidth of the FCLGA types is higher than that of the DFN-based types.
Even if the pure bandwidth improvement for the 2-pin type looks smaller compared to the 3-pin version, the improvement is only because of the different package: nearly 3 GHz=3.000.000.000 Hz. For the 3-pin device, the bandwidth improvement is nearly 200%, which was achieved by lower parasitic but also because of the opportunity the package offers to achieve better RF performance on different crystal layout concepts.
Return Loss
This package family also offers better return loss on each single line. As explained in blog1, the return loss gives information about how much of an incoming signal will be reflected in from the DUT and not pass through the device, though it does not contribute to good data quality on the receiver side of a transmission path.
The plots in Figure 3 show that, for both pin counts, the initial return loss at low frequencies is lower for the FCLGA product. The maximum return loss can be found with a slightly lower return loss, which also occurs at higher frequencies.
Cross-Talk
The last important single-ended S-Parameter plot is the cross-talk. Cross-talk of 2-pin devices does not matter as it does not generate pin-to-pin cross-talk. For the 3-pin devices, the cross-talk in comparison of DFN and FCLGA Types is shown in Figure 4.
For the products with 5 V VRWM, the new package platform offers much lower cross-talk than could be achieved with the DFN. It is 20 dB lower at frequencies below 10 GHz and exceeds the -20 dB range around 16.5 GHz.
Conclusion
The idea for a new package platform FCLGA was outlined and proven in this blog. Various single-ended S-Parameters were shown to demonstrate the benefits of the new package platform.
