GaN technology and specifically GaN-on-Silicon HEMT technology has become a key focus for power engineers over the last few years. Its promise to provide the high-power performance and high-frequency switching many applications are demanding is clear. However as commercial GaN FETs become more readily available one key question remains. Why cascode?
When we look at the physical and electrical nature of GaN HEMT devices, there is one obvious challenge. A GaN HEMT’s natural operation mode is as a depletion mode FET with a naturally “on” state. But as engineers we are used to working with naturally “off” devices, and the benefits this brings from a safety perspective. Therefore, a work around of the natural state of GaN HEMTs is needed to deliver naturally “off” operation. Currently there are two main approaches to this challenge. One is to change the structure of the device to operate in enhancement mode (or e-mode). The second is to use a stacked die cascode packaged device, with a naturally “off” low-voltage, low RDSon silicon MOSFET placed in series to the naturally “on” GaN HEMT device.
Stable high-power operation
Efficiency and thermal behaviour are comparable and positive for both e-mode and cascode, but that is where the similarities end. When it comes to device stability and ease of operation the cascode configuration provides the robust and reliable insulated (dielectric) gate structure of a silicon gate. That means the cascode GaN FET has an effective gate rating of ± 20 V (equal to existing silicon superjunction technology) and can be driven by standard cost-effective gate drivers with simple 0-10 or 12 V drive voltage. Yet it maintains the improved voltage blocking characteristics and switching performance of a naturally “on” GaN HEMT.
Having a tunable low-voltage MOSFET in series of course does technically increase the RDS(on) and QRR of a cascode-mode device. However, these increases are minimal or even inconsequential, especially when contrasted against the benefits that a robust and reliable insulated (dielectric) gate structure and high-performance body diode bring to GaN HEMT operation. For example, the increased RDS(on) is typically less than 10%, and still results in excellent HEMT RDS(on). As for QRR, the addition of the low-voltage MOSFET does add a very low value but that is an order of magnitude lower than a high-voltage silicon device with similar ratings to the high voltage HEMT.
For high-voltage / high-current / high-power applications and particularly automotive applications, robustness and reliability are critical. Cascode structures allow better AEC-Q101 automotive qualification and beyond, as the low-voltage silicon MOSFETs are automotive grade, meeting all automotive requirements. In addition, a high threshold voltage (Vth ~ 4 V) eliminates the potential of accidentally turning on due to the high dv/dt and di/dt, minimizing the risk of shoot through. Overall, this ensures stable application performance, which is further enhanced by robust low Vf reverse freewheeling performance.
Cascode - the obvious answer
Robust gate structure, high gate threshold voltage, simple gate drive, ultra-low reverse recovery loss, integrated very low Vf body diode, easy control of slew rate, large transient voltage capability and bidirectional topology. Taking everything into account, from Nexperia’s perspective the obvious answer for our 650 V GaN FETs for high-voltage / high-current / high-power applications was to go with cascode mode.
Of course, when normally “off” GaN HEMT devices are available with a robust, stable dielectric, high threshold voltage gate structure, then we will look again at which technology offers the best choice for our customers. Until that time, the question should not be “Why cascode?” but “How can I take advantage of 650 V GaN FETs?”.